A fractional pseudo random binary sequence for spur reduction in flying-adder frequency synthesizer

The clock spectrum contains spurious tones due to the periodic carries when fractional frequency control word is used in flying-adder frequency synthesizer. This paper presents a fractional pseudo random binary sequence (PRBS) technique for spur reduction. The proposed technique consists of an improved linear feedback shift register (LFSR) as pseudo random address generator, and a reduced read-before-write memory. A single path flying-adder frequency synthesizer and multiphase phase digitally controlled oscillator (DCO) has been fabricated in TSMC 0.18 μm 1P6M CMOS process to validate the proposed method. The spurious-free dynamic range (SFDR) is 47.3 dB as compared with 36.6 dB in traditional flying-adder frequency synthesizer at output frequency 37.9MHz, which has 10.7dB performance improvement.