DocumentCode :
1451472
Title :
An improved vector-reduction method
Author :
Sips, Henk J. ; Lin, Haixiang
Author_Institution :
Dept. of Appl. Phys., Delft Univ. of Technol., Netherlands
Volume :
40
Issue :
2
fYear :
1991
fDate :
2/1/1991 12:00:00 AM
Firstpage :
214
Lastpage :
217
Abstract :
A pipelined vector-reduction method that is based on L.M. Ni and K. Hwang´s (1985) symmetric and asymmetric reduction methods is discussed. It is shown that the proposed method is the fastest among known pipelined vector-reduction methods
Keywords :
digital arithmetic; pipeline processing; asymmetric reduction methods; pipelined vector-reduction method; symmetric reduction methods; Arithmetic; Computer applications; Feeds; Hardware; Merging; Parallel processing; Physics; Pipelines; Registers;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.73591
Filename :
73591
Link To Document :
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