• DocumentCode
    1452574
  • Title

    A 0.5-V 35-  \\mu W 85-dB DR Double-Sampled \\Delta \\Sigma Modulator for Audio Applications

  • Author

    Yang, Zhenglin ; Yao, Libin ; Lian, Yong

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore
  • Volume
    47
  • Issue
    3
  • fYear
    2012
  • fDate
    3/1/2012 12:00:00 AM
  • Firstpage
    722
  • Lastpage
    735
  • Abstract
    This paper presents a 0.5-V 1.5-bit double-sampled ΔΣ modulator for audio applications. Unlike existing double-sampled designs, the proposed double-sampled ΔΣ modulator employs an input-feedforward topology to reduce internal signal swings, thereby relaxing design requirements for the low-voltage building blocks and reducing distortion. Moreover, in order to avoid instability and noise shaping degradation, the proposed architecture restores the noise transfer function (NTF) of the double-sampled modulator to its single-sampled equivalent with the help of compensation loops. In the circuit implementation, the proposed fully-differential amplifier adopts an inverter output stage and a common-mode feedback (CMFB) circuit with a global feedback loop in order to reduce power consumption. A resistor-string-reference switch matrix based on a direct summation quantizer is used to simplify the analog compensation loop. The chip prototype has been fabricated in a 0.13-μm CMOS technology with a core area of 0.57 mm2. The measured results show that when operating from a 0.5-V supply and clocked at 1.25 MHz, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 81.7 dB, a peak signal-to-noise ratio (SNR) of 82.4 dB and a dynamic range (DR) of 85.0 dB while consuming 35.2 μW for a 20-kHz signal bandwidth.
  • Keywords
    CMOS integrated circuits; circuit feedback; differential amplifiers; invertors; low-power electronics; sigma-delta modulation; CMOS technology; analog compensation loop; audio application; bandwidth 20 kHz; common-mode feedback circuit; compensation loops; direct summation quantizer; distortion reduction; dynamic range double-sampled ΔΣ modulator; frequency 1.25 MHz; fully-differential amplifier; global feedback loop; input-feedforward topology; internal signal swing reduction; inverter output stage; noise shaping degradation; noise transfer function; power 35.2 muW; power consumption reduction; resistor-string-reference switch matrix; size 0.13 mum; voltage 0.5 V; word length 1.5 bit; Capacitors; Clocks; Modulation; Noise; Noise shaping; Quantization; Topology; CMOS technology; Delta-Sigma modulator; direct summation; double sampling; global-loop CMFB circuit; input feedforward; low power; low voltage; switched-capacitor circuit;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2011.2181677
  • Filename
    6155208