Improvement of latchup hardness by geometry and technology tuning

Author

Mazure, Carlos ; Reczek, Werner ; Takacs, Dezsoe ; Winnerl, Josef

Author_Institution

Siemens AG, Munich, West Germany

Volume

Issue

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1609

Lastpage

1615

Abstract

A latchup characterization method for CMOS technologies is presented. By separating the role of the parasitic bipolar transistors and the well and substrate shunt efficiencies, the interplay of geometry and technology becomes evident. An optimization of the device latchup hardness is achieved by partitioning the n⁺-p⁺ spacing with respect to the well. Substrate trigger currents depend on technological features such as substrate doping, well doping, and epilayer thickness

Keywords

CMOS integrated circuits; integrated circuit technology; CMOS technologies; epilayer thickness; geometry; latchup hardness; n⁺-p⁺ spacing; parasitic bipolar transistors; substrate doping; substrate shunt efficiencies; technology tuning; well doping; Bipolar transistors; CMOS technology; Critical current; Current measurement; Doping; Geometry; Helium; Research and development; Testing; Voltage control;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.7361

Filename

7361

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1452683