Improvement of latchup hardness by geometry and technology tuning

A latchup characterization method for CMOS technologies is presented. By separating the role of the parasitic bipolar transistors and the well and substrate shunt efficiencies, the interplay of geometry and technology becomes evident. An optimization of the device latchup hardness is achieved by partitioning the n⁺-p⁺ spacing with respect to the well. Substrate trigger currents depend on technological features such as substrate doping, well doping, and epilayer thickness