A system model for feedback control and analysis of yield: A multistep process model of effective gate length, poly line width, and IV parameters

Author

Rietman, Edward A. ; Whitlock, Stephen A. ; Beachy, Milton ; Roy, Andrew ; Willingham, Timothy L.

Author_Institution

Lucent Technol. Bell Labs., Orlando, FL, USA

Volume

14

Issue

1

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

32

Lastpage

47

Abstract

We present a large system model capable of producing Pareto charts for several yield metrics, including effective channel length, poly line width, I_on and I_sub. These Pareto charts enable us to target specific processes for improvement of the yield metric(s). Our neural network model has an accuracy of 80% and can be trained with a small data set to minimize the feedback time in the control loop for the yield. The system we describe has been implemented in a Lucent Technologies microelectronics lab in Orlando, FL

Keywords

Pareto distribution; feedback; integrated circuit yield; neural nets; process control; semiconductor process modelling; I-V characteristics; IC manufacturing; Pareto chart; Si; effective gate length; feedback control; multistep process model; neural network; polysilicon linewidth; system model; yield metric; Circuit testing; Control system analysis; Feedback control; Feedback loop; Machine learning; Manufacturing processes; Neural networks; Neurofeedback; Process control; Semiconductor device modeling;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.909653

Filename

909653