Title :
Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits
Author :
Pant, Pankaj ; De, Vivek K. ; Chatterjee, Abhijit
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
This paper demonstrates a new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths. The static, dynamic and short-circuit energy components are considered and an efficient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods.
Keywords :
CMOS logic circuits; circuit optimisation; integrated circuit design; logic design; low-power electronics; CMOS logic circuit; dynamic power dissipation; heuristic algorithm; low power design; minimization; optimization; power supply; short circuit energy; static power dissipation; threshold voltage; transistor size; Algorithm design and analysis; CMOS logic circuits; Clocks; Design optimization; Frequency; Logic devices; Optimization methods; Power dissipation; Power supplies; Threshold voltage;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
