Title :
The design and verification of a high-performance low-control-overhead asynchronous differential equation solver
Author :
Yun, Kenneth Y. ; Beerel, Peter A. ; Vakilotojar, Vida ; Dooply, Ayoob E. ; Arceo, Julio
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low-control-overhead which allows its average-case speed (tested at 22/spl deg/C and 3.3 V) to be 48% faster than any comparable synchronous design (designed to operate at 100/spl deg/C and 3 V for the slow process corner). The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed. In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control.
Keywords :
VLSI; asynchronous circuits; circuit optimisation; delays; differential equations; formal verification; integrated circuit design; logic CAD; timing; 22 degC; 3.3 V; asynchronous differential equation solver; average-case speed; benchmark circuit; completion sensing overhead; low-control-overhead design; protocol level; symbolic model checking techniques; timed distributed control; Asynchronous circuits; Clocks; Delay; Design optimization; Differential equations; Formal verification; Frequency; Protocols; Temperature; Timing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
