An Area-Efficient 0.13-μm CMOS Multiband WCDMA/HSDPA Receiver

In this paper, a multiband wideband code-division multiple access/high-speed downlink packet access direct-conversion receiver to cover all six Third-Generation Partnership Project bands is implemented in a 0.13-μm CMOS process. To reduce the increase of chip size due to implementation of the multimode multiband RF transceiver integrated circuit, a new integrated inductor structure sharing an inner diameter, a proposed mixed-type dc offset correction circuit, and a stacked structure of metal-insulator-metal and MOS capacitors is proposed. These silicon area reducing techniques can decrease the chip size by up to 30%. The measured full-path receiver performance is a noise figure of >3 dB, third-order intermodulation intercept point of > -17 dBm, and second-order intermodulation intercept point of > +30 dBm for all six bands. Its current consumption, including a frequency synthesizer, is 45 mA at 2.8-V supply voltage.