Title :
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability
Author :
Cheng, Lerong ; Gupta, Puneet ; Spanos, Costas J. ; Qian, Kun ; He, Lei
Author_Institution :
SanDisk Corp., Milpitas, CA, USA
fDate :
3/1/2011 12:00:00 AM
Abstract :
Modeling spatial variation is important for statistical analysis. Most existing works model spatial variation as spatially correlated random variables. We discuss process origins of spatial variability, all of which indicate that spatial variation comes from deterministic across-wafer variation, and purely random spatial variation is not significant. We analytically study the impact of across-wafer variation and show how it gives an appearance of correlation. We have developed a new die-level variation model considering deterministic across-wafer variation and derived the range of conditions under which ignoring spatial variation altogether may be acceptable. Experimental results show that for statistical timing and leakage analysis, our model is within 2% and 5% error from exact simulation result, respectively, while the error of the existing distance-based spatial variation model is up to 6.5% and 17%, respectively. Moreover, our new model is also faster than the spatial variation model for statistical timing analysis and faster for statistical leakage analysis.
Keywords :
integrated circuit modelling; statistical analysis; wafer-scale integration; deterministic across-wafer variation; die-level variation modeling; distance-based spatial variation model; spatially-correlated random variables; statistical leakage analysis; statistical timing analysis; Analytical models; Correlation; Mathematical model; Random variables; Semiconductor device modeling; Systematics; Timing; Leakage analysis; SSTA; spatial correlation; timing analysis; yield modeling;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2010.2089568