Title :
A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis
Author :
Del Barrio, Alberto A. ; Memik, Seda Ogrenci ; Molina, María C. ; Mendías, José M. ; Hermida, Román
Author_Institution :
Dept. of Comput. Archit. & Syst. Eng., Complutense Univ. of Madrid, Madrid, Spain
fDate :
3/1/2011 12:00:00 AM
Abstract :
Speculative functional units (SFUs) are arithmetic functional units that operate using a predictor for the carry signal. The carry prediction helps to shorten the critical path of the functional unit. The average case performance of these units is determined by the hit rate of the prediction. In case of mispredictions, the SFUs need to be coordinated by the datapath control mechanism to perform corrections and to maintain the datapath in the correct state. Devising a control mechanism for correcting mispredictions without adversely impacting overall performance is the most important challenge. In this paper, we present techniques for designing a datapath controller for seamless deployment of SFUs in high level synthesis. We have developed two techniques based on two main control paradigms: centralized and distributed control. The centralized approach stops the execution of the entire datapath for each misprediction and resumes execution once the correct value of the carry is known. The distributed approach decouples the functional unit suffering from the misprediction from the rest of the datapath. Hence, it allows the remainder of the functional units to carry on execution and be at different scheduling states at different times. We tested datapaths utilizing both linear structures and logarithmic structures for speculative arithmetic functional units. Our results show that it is possible to reduce execution time by as much as 38% (33% on average) for linear structures and by as much as 37.2% (25% on average) for logarithmic structures.
Keywords :
carry logic; centralised control; control system synthesis; distributed control; high level synthesis; processor scheduling; carry signal predictor; centralized control; datapath control mechanism; datapath controller; distributed controller; high level synthesis; linear structure; logarithmic structure; speculative arithmetic functional unit; Adders; Computer architecture; Delay; Dynamic scheduling; High level synthesis; Program processors; Registers; Dynamic scheduling; HLS; speculation;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2010.2089565