Title :
Deeper SSC estimator used as CDR
Author :
Yaming Zhang ; Weixin Gai
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
A deeper SSC estimator used as a CDR with a low power mechanism based on third-order architecture is proposed to suppress the disadvantage of the conventional third-order CDR happening at the switching points of SSC (spread spectrum clocking). For 10 Gbit/s data speed, the depth of its SSC tracking may be up to 10000 ppm at 30 kHz which helps to reduce more EMI.
Keywords :
analogue circuits; clock and data recovery circuits; electromagnetic interference; frequency estimation; interference suppression; low-power electronics; phase locked loops; EMI reduction; SSC tracking; analogue PLL based clock and data recovery; bit rate 10 Gbit/s; deeper SSC estimator; frequency 30 kHz; frequency estimation; low power mechanism; spread spectrum clocking; third-order CDR; third-order architecture;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2012.4086
