High-performance flexible all-digital quadrature up and down converter chip

Author

Pasko, R. ; Rijnders, Luc ; Schaumont, Patrick R. ; Vernalde, Serge A. ; Durackova, D.

Author_Institution

Inter-Univ. Microelectron. Centre, Leuven, Belgium

Volume

36

Issue

3

fYear

2001

fDate

3/1/2001 12:00:00 AM

Firstpage

408

Lastpage

416

Abstract

In this paper, the design of an all-digital quadrature up and down converter with high accuracy and flexible intermediate frequency (IF) settings is presented. The signal up or down conversion is achieved by interpolation and decimation combined with a programmable anti-alias filter to preserve the selected frequency band during the sample rate conversion. This way a high-speed solution with low power consumption is obtained. A novel technique, based on the use of canonic signed digit (CSD) code, was utilized to implement the programmable anti-alias filter structure. The resulting chip fabricated in a 0.5-μm CMOS process is capable of handling sample rates up to 160 megasamples per second (MSPS) and is suitable for coaxial access network modem applications

Keywords

CMOS digital integrated circuits; frequency convertors; high-speed integrated circuits; interpolation; low-power electronics; programmable filters; 0.5 micron; CMOS chip; IF setting; all-digital quadrature frequency converter; canonic signed digit code; coaxial access network modem; decimation; high-speed low-power IC; interpolation; programmable anti-alias filter; sample rate conversion; Baseband; CMOS process; Circuits; Coaxial components; Energy consumption; Finite impulse response filter; Frequency conversion; Hardware; Interpolation; Radio frequency;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.910479

Filename

910479