DocumentCode :
1453494
Title :
A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop
Author :
Lin, Tsung-Hsien ; Kaiser, William J.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Volume :
36
Issue :
3
fYear :
2001
fDate :
3/1/2001 12:00:00 AM
Firstpage :
424
Lastpage :
431
Abstract :
A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-μm CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (KVCO) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply
Keywords :
CMOS analogue integrated circuits; UHF integrated circuits; circuit noise; circuit tuning; frequency synthesizers; phase locked loops; phase noise; switched capacitor networks; varactors; voltage-controlled oscillators; 0.6 micron; 2.5 mA; 3 V; 900 MHz; CMOS frequency synthesizer; CMOS varactor continuous-tuning; VCO gain; automatic SC tuning loop; automatic switched-capacitor discrete-tuning loop; noise performance; offset frequency; overall frequency tuning range; phase noise; reference spurs; wireless integrated network sensors; CMOS technology; Costs; Frequency shift keying; Frequency synthesizers; Phase locked loops; Transceivers; Tuning; Voltage-controlled oscillators; Wireless communication; Wireless sensor networks;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.910481
Filename :
910481
Link To Document :
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