Title :
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield
Author :
Noda, Kentaro ; Takeda, Kenji ; Matsui, K. ; Kawamoto, Hiroaki ; Ikezawa, N. ; Aimoto, Y. ; Nakamura, N. ; Iwasaki, Takuya ; Toyoshima, Hisashi ; Horiuchi, T.K.
Author_Institution :
ULSI Device Dev. Div., NEC Corp., Kanagawa
fDate :
3/1/2001 12:00:00 AM
Abstract :
We have developed two schemes for improving access speed and reliability of a loadless four-transistor (LL4T) SRAM cell: a dual-layered twisted bitline scheme, which reduces coupling capacitance between adjacent bitlines in order to achieve highspeed READ/WRITE operations, and a triple-well shield, which protects the memory cell from substrate noise and alpha particles. We incorporated these schemes in a high-performance 0.18-μm-generation CMOS technology and fabricated a 16-Mb SRAM macro with a 2.18-μm2 memory cell. The macro size of the LL4T-SRAM is 56 mm2, which is 30% to 40% smaller than a conventional six-transistor SRAM when compared with the same access speed. The developed macro functions at 500 MHz and has an access time of 2.0 ns. The standby current has been reduced to 25 μA/Mb with a low-leakage nMOSFET in the memory cell
Keywords :
CMOS memory circuits; SRAM chips; alpha-particle effects; high-speed integrated circuits; integrated circuit noise; integrated circuit reliability; leakage currents; memory architecture; 0.18 micron; 16 Mbit; 2.0 ns; 500 MHz; CMOS; access speed; alpha particles; coupling capacitance; high-speed loadless four-transistor SRAM macro; low-leakage nMOSFET; reliability; standby current; substrate noise; triple-well shield; twisted bitline architecture; CMOS logic circuits; CMOS technology; Capacitance; Costs; Fabrication; Frequency; Indium tin oxide; National electric code; Random access memory; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
