A 20-bit 25-kHz delta-sigma A/D converter utilizing a frequency-shaped chopper stabilization scheme

Author

Wang, Chris Binan

Author_Institution

Burr-Brown Corp., Tucson, AZ, USA

Volume

36

Issue

3

fYear

2001

fDate

3/1/2001 12:00:00 AM

Firstpage

566

Lastpage

569

Abstract

A 20-bit delta-sigma A/D converter is implemented in a 0.6-μm CMOS process with a single 5-V supply. It provides a 25-kHz data rate for high-speed dc measurement while maintaining good the performance required for accurate dc measurement such as noise, linearity and drift. The front-end programmable gain amplifier (PGA) allows the user to optimize their system for different input ranges. Offset and finite gain compensation are used in the PGA section to reduce offset and improve linearity performance of the amplifier. In the delta-sigma converter section, low frequency error reduction is achieved through the use of chopper stabilization technique. A frequency-shaped chopper stabilization scheme is used to alleviate the intermodulation tone problem commonly associated with the use of the fixed rate chopping in delta-sigma modulators. This A/D converter achieves 2.5 ppm RMS noise and 12 ppm INL at gain of one

Keywords

CMOS integrated circuits; analogue-digital conversion; choppers (circuits); circuit stability; delta-sigma modulation; high-speed integrated circuits; integrated circuit noise; 0.6 micron; 20 bit; 25 kHz; 5 V; A/D converter; CMOS chip; delta-sigma modulator; drift; finite gain compensation; frequency-shaped chopper stabilization; high-speed DC measurement; intermodulation; linearity; noise; offset compensation; programmable gain amplifier; Choppers; Delta modulation; Digital filters; Digital modulation; Electronics packaging; Finite impulse response filter; Frequency conversion; Linearity; Low-frequency noise; Noise measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.910497

Filename

910497