• DocumentCode
    1454146
  • Title

    Testing large analog/digital signal processing chips

  • Author

    Freeman, Smith

  • Author_Institution
    David Sarnoff Res. Center Inc., Princeton, NJ, USA
  • Volume
    36
  • Issue
    4
  • fYear
    1990
  • fDate
    11/1/1990 12:00:00 AM
  • Firstpage
    813
  • Lastpage
    818
  • Abstract
    An approach to testing VLSI chips with analog IO and internal digital signal processing has been successfully demonstrated in several custom designs. Functional testing of analog circuitry was combined with high fault coverage digital testing by use of a multipurpose test bus. The approach provides at-speed tests of functional character, which are to be preferred for timing verification as well as for test thoroughness and device reliability. Analog interfaces and severe pin limitations can be accommodated, and no performance degradation need be accepted
  • Keywords
    VLSI; built-in self test; digital signal processing chips; integrated circuit testing; DSP chips; VLSI chips testing; analog IO; analog circuitry; analog signal processing chips; custom designs; device reliability; fault coverage digital testing; functional testing; multipurpose test bus; timing verification; Circuit faults; Circuit testing; Digital signal processing chips; Electronic equipment testing; Fault detection; Logic testing; Pins; System testing; Test pattern generators; Timing;
  • fLanguage
    English
  • Journal_Title
    Consumer Electronics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-3063
  • Type

    jour

  • DOI
    10.1109/30.61560
  • Filename
    61560