Increasing Reliability of FPGA-Based Adaptive Equalizers in the Presence of Single Event Upsets

Reliability is a major concern for electronic circuits, especially for those that operate in harsh environments. One source of problems are Single Event Upsets (SEU), which change the value of flip flops and memory cells. SEUs are a major issue for SRAM-based Field Programmable Gate Arrays (FPGAs), as they may alter the circuit functionality, creating errors that will only be removed if the device is reprogrammed. The cost of traditional techniques to deal with SEUs, like triplication, can be excessive in some applications. One example are Space systems, in which power consumption and weight are limited. In those cases, the use of ad hoc protection techniques that can reduce the cost is interesting. In this paper, new protection techniques for adaptive equalizers implemented in SRAM-based FPGAs are presented. The proposed techniques use the knowledge of the equalizer to provide effective protection at a lower cost. The results show a reduction of up to 70% in the use of resources in comparison to the commercial XTMR solution.