A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

Author

Terada, Kazuo ; Ishijima, Toshiyuki ; Kubota, Taishi ; Sakao, Masato

Author_Institution

NEC Corp., Shimokuzawa, Japan

Volume

37

Issue

9

fYear

1990

fDate

9/1/1990 12:00:00 AM

Firstpage

2052

Lastpage

2057

Abstract

A new dynamic RAM (DRAM) cell structure and its fabrication technology are proposed. The proposed DRAM cell consists of a transistor on a lateral epitaxial silicon layer (TOLE) and a stacked capacitor formed in a trench. It can achieve high immunity to alpha-particle-induced noise and a low parasitic bit-line capacitance. The TOLE structure is produced by a silicon-on-insulator fabrication technology newly developed by combining epitaxial lateral overgrowth and preferential polishing. Reasonable electrical characteristics for the TOLE and high immunity against alpha-particle disturbance for the TOLE cell were confirmed

Keywords

CMOS integrated circuits; alpha-particle effects; integrated circuit technology; integrated memory circuits; random-access storage; semiconductor epitaxial layers; semiconductor-insulator boundaries; DRAM cell; SOI technology; Si epitaxial layer; TOLE structure; alpha-particle-induced noise; dynamic RAM; electrical characteristics; epitaxial lateral overgrowth; fabrication technology; parasitic bit-line capacitance; preferential polishing; stacked capacitor; transistor on lateral epitaxial silicon layer; twin well CMOS; Capacitors; Electric variables; Electrodes; Fabrication; Insulation; Parasitic capacitance; Random access memory; Semiconductor films; Silicon on insulator technology; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.57168

Filename

57168