• DocumentCode
    1454926
  • Title

    Asynchronous parallel prefix computation

  • Author

    Manohar, Rajit ; Tierno, José A.

  • Author_Institution
    Dept. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
  • Volume
    47
  • Issue
    11
  • fYear
    1998
  • fDate
    11/1/1998 12:00:00 AM
  • Firstpage
    1244
  • Lastpage
    1252
  • Abstract
    The prefix problem is to compute all the products x1⊗x2⊗…⊗xk, for 1⩽k⩽n, where ⊗ is an associative binary operation. We start with an asynchronous circuit to solve this problem with O(log n) latency and O(n log n) circuit size, with O(n) ⊗-operations in the circuit. Our contributions are: (1) a modification to the circuit that improves its average-case latency from O(log n) to O(log log n) time, and (2) a further modification that allows the circuit to run at full-throughput, i.e., with constant response time. The construction can be used to obtain an asynchronous adder with O(log n) worst-case latency and O(log log n) average-case latency
  • Keywords
    adders; asynchronous circuits; digital arithmetic; parallel algorithms; associative binary operation; asynchronous adder; asynchronous circuit; asynchronous parallel prefix computation; average-case latency; worst-case latency; Adders; Asynchronous circuits; Cogeneration; Concrete; Concurrent computing; Delay; Hardware; Pipeline processing;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.736437
  • Filename
    736437