An all-electrical floating-gate transmission line model technique for measuring source resistance in heterostructure field-effect transistors

A new technique for determining the parasitic source resistance in heterostructure field-effect transistors (HFETs) is presented. The new technique is an improvement of the floating-gate transmission line model and uses purely electrical measurements; there is no need to determine any critical lengths optically or by scanning electron microscopy. The technique is demonstrated in In_0.52Al_0.48As/n⁺-In_0.53Ga _0.47As metal-insulator-doped semiconductor field-effect transistors (MIDFETs). The new technique holds great promise for automated measurements of source resistance in a manufacturing environment