Tamper Resistance Verification Method for Consumer Security Products

Consumer security products handling confidential information are secured by encrypting data. The encryption standard, which has been widely diffused in recent years, is certified that its decryption is computationally impossible. However, it was recently reported that even if an encryption algorithm is theoretically secured, when the algorithm is incorporated into hardware, confidential information about the algorithm could be improperly revealed using power consumption data when the hardware is operated. Such improper specifications are generally called side-channel attacks. Therefore, when an encryption algorithm is incorporated into hardware, evaluation of the resistance against power analysis attacks (tamper resistance) becomes important in the design stage of the circuit. The present study proposes a new method for efficient verification of tamper resistance against power analysis attacks when designing a cryptography circuit. The validity of the proposed method is confirmed using design data of an experimentally produced chip of the advanced encryption standard (AES).