Title :
S-parameter measurement prediction for bipolar transistors using a physical device simulator
Author :
Yuan, Jiann-shiun ; Eisenstadt, William R.
Author_Institution :
Dept. of Electr. Eng., Florida Univ., Gainesville, FL, USA
fDate :
10/1/1988 12:00:00 AM
Abstract :
S-parameter data characterizing bipolar IC test structures (including layout parasitics) are derived from two-dimensional device simulations of a submicrometer emitter bipolar transistor (BJT). The modeling used for the calculation of the BJT test structure S-parameter response is reported. The effects of interconnect and bond pads used in the IC test structure layout are evaluated. In addition, a two-layer metal interconnect-based test structure with very low signal loss is proposed. This result has applications in: (1) designing BJT test structures for IC technologies, (2) supplementing existing two-port S-parameter measurements to provide three-port characterization, and (3) evaluating the accuracy of on-chip S-parameter calibration techniques for specific IC test structure layouts
Keywords :
bipolar integrated circuits; bipolar transistors; integrated circuit testing; semiconductor device models; IC test structure layout; S-parameter data; bipolar transistors; bond pads; calibration techniques; interconnect; layout parasitics; physical device simulator; two-dimensional device simulations; two-layer metal interconnect-based test structure; very low signal loss; Application specific integrated circuits; Bipolar transistors; Bonding; Calibration; Circuit testing; Integrated circuit layout; Integrated circuit modeling; Integrated circuit testing; Predictive models; Scattering parameters;
Journal_Title :
Electron Devices, IEEE Transactions on
