Title :
Multiobjective optimization of VLSI interconnect parameters
Author :
Anand, M.B. ; Shibata, Hideki ; Kakumu, Masakazu
Author_Institution :
ULSI Process Eng. Lab., Toshiba Corp., Yokohama, Japan
fDate :
12/1/1998 12:00:00 AM
Abstract :
The significant role played by interconnects in determining the speed and chip size of very-large-scale integrated circuits (VLSI) necessitates the development of new processes and tools for almost every device generation. Since such development usually requires lead times of several years, it has become essential to know, several years in advance, the various interconnect parameters for a particular generation. In this paper, a tool for optimizing interconnect parameters is presented. The formulation of an optimization problem that can be solved using standard algorithms is shown to be possible, and the optimization results obtained for future device generations are discussed. These results can be used to construct an interconnect technology roadmap. Last, shortcomings of and possible improvements to existing system-level critical path models are discussed
Keywords :
VLSI; circuit CAD; circuit optimisation; critical path analysis; integrated circuit design; integrated circuit interconnections; VLSI; chip size; interconnect parameters; multiobjective optimization; standard algorithms; system-level critical path models; technology roadmap; Dielectric materials; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit synthesis; Integrated circuit technology; Large scale integration; Parasitic capacitance; Power system modeling; Very large scale integration; Wire;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
