Title :
Low-power state assignment targeting two- and multilevel logic implementations
Author :
Tsui, Chi-ying ; Pedram, Massoud ; Despain, Alvin M.
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Clear Water Bay, Hong Kong
fDate :
12/1/1998 12:00:00 AM
Abstract :
The problem of minimizing power consumption during the state encoding of a finite-state machine is addressed. A new power cost model for state encoding is proposed, and encoding techniques that minimize this power cost for two- and multilevel logic implementations are described. These techniques are compared with those that minimize area or the switching activity at the present state bits. Experimental results show significant improvements
Keywords :
finite state machines; logic design; low-power electronics; minimisation of switching nets; multivalued logic circuits; state assignment; area; finite state machine; low power state assignment; minimization; multilevel logic; power consumption; power cost model; state encoding; switching activity; two-level logic; Circuit simulation; Computational modeling; Costs; Electronic circuits; Encoding; Energy consumption; Hypercubes; Logic; Minimization; Simulated annealing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
