DocumentCode :
1456451
Title :
Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages
Author :
Lindert, Nick ; Sugii, Toshihiro ; Tang, Stephen ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Volume :
34
Issue :
1
fYear :
1999
fDate :
1/1/1999 12:00:00 AM
Firstpage :
85
Lastpage :
89
Abstract :
We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed
Keywords :
MOS logic circuits; delays; logic gates; low-power electronics; 0.5 to 1.5 V; body bias modulation; delay improvement; dynamic adjustment; dynamic threshold pass-transistor logic; dynamic threshold voltage MOSFET logic styles; pass-gate comparison; pass-transistor restoration schemes; power supply voltage scaling; threshold voltage; ultralow-power use; Degradation; Delay; Dynamic voltage scaling; Guidelines; Logic circuits; Low voltage; MOSFET circuits; Microprocessors; Power supplies; Threshold voltage;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.736659
Filename :
736659
Link To Document :
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