Title :
A four-phase handshaking asynchronous static RAM design for self-timed systems
Author :
Sit, Vincent Wing-Yun ; Choy, Chiu-Sing ; Chan, Cheong-Fat
Author_Institution :
Chinese Univ. of Hong Kong, Shatin, Hong Kong
fDate :
1/1/1999 12:00:00 AM
Abstract :
The motivation of designing asynchronous memory arises from the recent development of asynchronous processors. As different from the conventional design, the proposed asynchronous static RAM can: (1) communicate with other asynchronous systems based on a four-phase handshaking control protocol; and (2) generate the read/write completion signals with increased average speed by the variable bit-line load concept. The techniques investigated include (1) dual-rail voltage sensing completion detection for read operation and (2) multiple delays completion generation for write operation. In this paper, the performances of these techniques are evaluated for 1 Mb memory with four regions of bit-line segmentation. The simulated and measured results are presented and compared
Keywords :
CMOS memory circuits; SRAM chips; asynchronous circuits; memory protocols; timing; 1 Mbit; asynchronous SRAM design; asynchronous memory; asynchronous static RAM; bit-line segmentation; dual-rail voltage sensing completion detection; four-phase handshaking control protocol; multiple delays completion generation; read operation; read/write completion signals; self-timed systems; variable bit-line load; write operation; Circuits; Clocks; Control systems; Delay; Microprocessors; Random access memory; Read-write memory; Signal design; Signal generators; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
