A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC)

Author

Soares, J. Navarro, Jr. ; Van Noije, W.A.M.

Author_Institution

Escola Politecnica, Sao Paulo Univ., Brazil

Volume

34

Issue

1

fYear

1999

fDate

1/1/1999 12:00:00 AM

Firstpage

97

Lastpage

102

Abstract

The implementation of a dual-modulus prescaler (divide by 128/129) using an extension of the true-single-phase-clock (TSPC) technique, the extended TSPC (E-TSPC), is presented. The E-TSPC consists of a set of composition rules for single-phase-clock circuits employing static, dynamic, latch, data-precharged, and NMOS-like CMOS blocks. The composition rules, as well as the CMOS blocks, are described and discussed. The experimental results of the complete dual-modulus prescaler, implemented in a 0.8 μm CMOS process, show a maximum 1.59 GHz operation rate at 5 V with 12.8 mW power consumption. They are compared with the results from other recent implementations showing that the proposed E-TSPC circuit can reach high speed with both smaller area and lower power consumption

Keywords

CMOS logic circuits; high-speed integrated circuits; prescalers; timing; 0.8 micron; 1.59 to 1.6 GHz; 12.8 mW; 5 V; CMOS circuit technique; composition rules; dual modulus prescaler; extended TSPC; high speed operation; power consumption reduction; submicron CMOS process; true-single-phase-clock; CMOS digital integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Energy consumption; Latches; Rails; Very large scale integration; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.736661

Filename

736661