A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC´s

Author

Jen, Steve H. ; Sheu, Bing J. ; Park, Yoondong

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

34

Issue

1

fYear

1999

fDate

1/1/1999 12:00:00 AM

Firstpage

103

Lastpage

106

Abstract

A unified modeling approach for the submicrometer MOS transistor charge/capacitance characteristics in all operation regions is presented. Development of this MOS charge model is based on the charge-density approximation to reduce the complexity of the analytical expression. To model the charge density more accurately, the conductance-degradation coefficient is determined by the derivative of drain-to-source saturation voltage with respect to gate-to-channel potential. The unified charge densities in gate, channel, and bulk regions are obtained with the assistance of the sigmoid, hyperbola, and exponential interpolation techniques. Good agreement between the measurement data and simulation results is obtained

Keywords

CMOS integrated circuits; MOSFET; capacitance; electric charge; integrated circuit modelling; interpolation; mixed analogue-digital integrated circuits; semiconductor device models; bulk region; channel region; charge-density approximation; conductance-degradation coefficient; drain-to-source saturation voltage; exponential interpolation technique; gate region; gate-to-channel potential; hyperbola interpolation technique; mixed-signal ICs; sigmoid interpolation technique; submicron MOS transistor model; unified charge/capacitance model; CMOS technology; Capacitance; Capacitance-voltage characteristics; Integrated circuit modeling; Integrated circuit technology; Interpolation; Linear approximation; MOSFETs; Semiconductor device modeling; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.736662

Filename

736662