Improving Memory Reliability Against Soft Errors Using Block Parity

Memory reliability is an important issue. The continuous scaling of transistor technology enables the use of larger memories making soft errors more likely to occur. To ensure that those errors do not cause data corruption, error correcting codes (ECC) are commonly used. Single error correction-double error detection codes (SEC-DED) are typically implemented in each memory word, so that a single error in a word can be corrected and two errors can be detected. In this paper, a technique to improve the reliability of memories that use SEC-DED is studied. The proposed technique shows that it is possible to substantially improve the mean time to failure (MTTF) of the memory at the cost of increasing the access time for writing operations.