Title :
Direct measurement of ingress and egress latency on 1000Base-T Gigabit Ethernet links
Author_Institution :
InterOperability Lab., Univ. of New Hampshire, Durham, NH, USA
Abstract :
Any error in a physical layer´s asymmetry corrections for egress and ingress latency can result in uncorrectable timing error. These asymmetries increase the timing inaccuracy of any PTP system. A technique to directly measure the ingress and egress latencies of a 1000Base-T Gigabit Ethernet physical layer is presented.
Keywords :
local area networks; protocols; synchronisation; Ethernet links; Ethernet physical layer; PTP system; egress latency; ingress latency; physical layer asymmetry corrections; precision time protocol; timing error; Accuracy; Clocks; Delays; Hardware; Physical layer; Transmitters;
Conference_Titel :
Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS), 2014 IEEE International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4799-2698-5
DOI :
10.1109/ISPCS.2014.6948531
