Title :
Fixed-point error analysis and word length optimization of 8×8 IDCT architectures
Author :
Kim, Seehyun ; Sung, Wonyong
Author_Institution :
Inf. Technol. Lab., LG Corp. Inst. of Technol., Seoul, South Korea
fDate :
12/1/1998 12:00:00 AM
Abstract :
Complete fixed-point error models that include the coefficient quantization are derived for two popular 8×8 two-dimensional (2-D) IDCT architectures; one is based on distributed arithmetic, and the other is the multiplier-adder chain. The error models are evaluated in the integer domain to accurately measure the effects of rounding. The analysis results show that the overall mean-square error performance (OMSE) is the most critical condition for meeting the IEEE specification (IEEE Std. 1180-1990) when the rounding scheme is employed. On the other hand, the mean error effects (OME and PME) are dominant for truncation. Finally, the analysis results are compared with those of bit-accurate simulation
Keywords :
IEEE standards; VLSI; adders; circuit optimisation; digital signal processing chips; discrete cosine transforms; distributed arithmetic; fixed point arithmetic; image processing; inverse problems; mean square error methods; multiplying circuits; roundoff errors; telecommunication standards; video signal processing; 2D IDCT architectures; IEEE specification; IEEE standard 1180-1990; VLSI; bit-accurate simulation; coefficient quantization; distributed arithmetic; fixed-point error analysis; fixed-point error models; image processing standards; integer domain; multiplier-adder chain; overall mean-square error performance; peak mean error; rounding effects; truncation; video processing standards; word length optimization; Analytical models; Discrete cosine transforms; Error analysis; Fixed-point arithmetic; Helium; Performance analysis; Quantization; Testing; Two dimensional displays; Very large scale integration;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
