Title :
A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement
Author :
Lee, Woojun ; Choi, Woo Young
Author_Institution :
Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea
fDate :
5/1/2011 12:00:00 AM
Abstract :
This paper proposes a silicon-with-partially-insulating-layer-on-silicon-on-insulator (SISOI) one-transistor dynamic random access memory (1T DRAM) cell to increase data retention time. A conventional 1T DRAM cell has a data retention problem because it stores holes in an SOI layer, which is not separated from the source/drain region. However, the proposed SISOI 1T DRAM cell can keep holes electrically separated from the source/drain region, which leads to the increase of data retention time.
Keywords :
DRAM chips; logic design; silicon-on-insulator; 1T DRAM cell; SISOI; Si; data retention time improvement; one-transistor dynamic random access memory cell; silicon-with-partially-insulating-layer-on-silicon-on-insulator DRAM; CMOS process; Capacitors; DRAM chips; Germanium silicon alloys; Impact ionization; Permission; Random access memory; Silicon germanium; Silicon on insulator technology; Spontaneous emission; Capacitorless 1T DRAM cell; Shockley–Read–Hall (SRH) recombination; data retention time; silicon-with-partially-insulating-layer-on-silicon-on-insulator (SISOI) 1T DRAM cell;
Journal_Title :
Nanotechnology, IEEE Transactions on
DOI :
10.1109/TNANO.2010.2046743
