DocumentCode :
1457154
Title :
Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness
Author :
Yun Ye ; Liu, F. ; Min Chen ; Nassif, S. ; Yu Cao
Author_Institution :
Dept. of Electr. Engi neering, Arizona State Univ., Tempe, AZ, USA
Volume :
19
Issue :
6
fYear :
2011
fDate :
6/1/2011 12:00:00 AM
Firstpage :
987
Lastpage :
996
Abstract :
The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations which are too expensive in computation for statistical design. In this work, we develop an efficient SPICE simulation method and statistical variation model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by lithography and the etching process. By understanding the physical principles of atomistic simulations, we: 1) identify the appropriate method to divide a nonuniform gate into slices in order to map those fluctuations into the device model; 2) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth ; 3) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations; and 4) investigate the interaction with non-rectangular gate (NRG) and reverse narrow width effect (RNWE). The proposed SPICE simulation method is validated with atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, helping shed light on the challenges of future robust circuit design.
Keywords :
MOSFET; SPICE; circuit simulation; etching; leakage currents; lithography; nanoelectronics; semiconductor device models; semiconductor doping; statistical analysis; transistor circuits; SPICE simulation; atomistic simulation; circuit design; device model; device output current; etching process; gate length fluctuation; gate size; leakage current; line-edge roughness; nanoscale transistor; nonrectangular gate; postlithography gate geometry; random dopant fluctuation; reverse narrow width effect; saturation current; statistical variation model; threshold variation; threshold voltage; Analytical models; Computational modeling; Etching; Fluctuations; Leakage current; Lithography; Predictive models; SPICE; Semiconductor process modeling; Threshold voltage; Atomistic simulation; gate slicing; line-edge roughness; non-rectangular gate; random dopant fluctuations; threshold voltage; variation;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2010.2043694
Filename :
5439902
Link To Document :
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