A VLSI for real-time linear operations and transforms

Author

Newel, Matthew ; Rasure, John

Author_Institution

Dept. of Electr. & Comput. Eng., New Mexico Univ., Albuquerque, NM, USA

Volume

39

Issue

8

fYear

1991

fDate

8/1/1991 12:00:00 AM

Firstpage

1914

Lastpage

1917

Abstract

A VLSI system, utilizing 16 systolic array multipliers, designed to compute vector-matrix products at a rate of 640×10⁶ MACs is presented. The 448,000-transistor, 1.6-μm CMOS device incorporates a dual timing scheme which allows multiplexing of hardware units over identical operations. This hardware balances maximum internal operating frequency with external data bandwidth and results in an improved ration of the signal throughput to silicon area. This system has wide application because of its ability to compute correlation, convolution, linear transforms, and connections in multilayer perceptrons

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; digital signal processing chips; multiplying circuits; systolic arrays; 1.6 micron; ASIC; CMOS device; DSP chip; VLSI; convolution; correlation; dual timing scheme; linear transforms; multilayer perceptrons; multiplexing; real-time linear operations; signal processing algorithms; systolic array multipliers; vector-matrix products; Bandwidth; Convolution; Frequency; Hardware; Multilayer perceptrons; Silicon; Systolic arrays; Throughput; Timing; Very large scale integration;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.91166

Filename

91166