Surface-states effects on GaAs FET electrical performance

We analyzed the effects of surface-states on GaAs FET electrical performance with a two-dimensional (2-D) device simulator that used a surface-state model based on Shockley-Read-Hall (SRH) statistics. We found that under typical FET operating conditions, electron-trap-type surface-states pin the surface potential to the electron quasi-Fermi level (that is, the n-type channel potential), whereas hole-trap-type surface-states pin it to the hole quasi-Fermi level (that is, the gate potential). This difference affects both the electric-field distribution along the channel and the drain current values. The transient responses to step-bias application at the gate and at the drain showed slow transients due to the surface-states, but the directions of the shifts were opposite for the different trap-types. We explain these phenomena using a theory based on Shockley-Read-Hall statistics for the surface-states