Title :
Obtaining schedules for digital systems
Author :
Jagadish, H.V. ; Kailath, Thomas
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
fDate :
10/1/1991 12:00:00 AM
Abstract :
A systematic technique is presented to derive correct schedules for a synchronous digital system, given a signal flow graph for an algorithm. It is also shown how to use this technique to derive designs that are optimal in having the lowest latency, the highest throughput, or the smallest number of registers. The same technique can also be used to verify digital systems that have already been designed
Keywords :
computerised signal processing; digital systems; scheduling; correct schedules; latency; signal flow graph; signal processing; synchronous digital system; systematic technique; throughput; Algorithm design and analysis; Circuit synthesis; Delay; Digital systems; Flow graphs; Hardware; Scheduling algorithm; Signal design; Signal processing; Signal processing algorithms;
Journal_Title :
Signal Processing, IEEE Transactions on
