DocumentCode
1458555
Title
Interconnect Design for Subthreshold Circuits
Author
Pable, Sachin D. ; Hasan, Mohd
Author_Institution
Dept. of Electron. Eng., Aligarh Muslim Univ., Aligarh, India
Volume
11
Issue
3
fYear
2012
fDate
5/1/2012 12:00:00 AM
Firstpage
633
Lastpage
639
Abstract
Designing ultralow-power (ULP) efficient very large scale integration digital circuits have received widespread attention due to the rapid growth of portable applications. Device operating in subthreshold region has a strong potential toward satisfying the ULP conditions of portable systems. This paper mainly investigated and compared the performance of single-wall carbon nanotube (SWCNT), Cu, and mixed CNT bundle interconnects for different interconnect lengths and biasing levels under subthreshold conditions. It proposes that individual SWCNT can be used for short and intermediate length interconnects at different bias points in the subthreshold region due to less critical interconnect resistance contrary to superthreshold region. Furthermore, performance analysis of global interconnect shows that in moderate subthreshold region, scaled Cu interconnect performs better than individual SWCNT and mixed CNT bundle, whereas in deep subthreshold region individual SWCNT is still better.
Keywords
VLSI; carbon nanotubes; integrated circuit interconnections; ULP condition; biasing level; critical interconnect resistance; interconnect design; interconnect length; portable systems; single wall carbon nanotube; subthreshold circuit; superthreshold region; very large scale integration digital circuits; Copper; Delay; Integrated circuit interconnections; Performance evaluation; Quantum capacitance; Resistance; Aspect ratio scaling; interconnect; mixed carbon nanotube (CNT) bundle; single-wall carbon nanotube (SWCNT); subthreshold;
fLanguage
English
Journal_Title
Nanotechnology, IEEE Transactions on
Publisher
ieee
ISSN
1536-125X
Type
jour
DOI
10.1109/TNANO.2012.2189015
Filename
6158605
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