• DocumentCode
    1458660
  • Title

    Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect Transistors

  • Author

    Liu, Lu ; Mohata, Dheeraj ; Datta, Suman

  • Author_Institution
    Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA, USA
  • Volume
    59
  • Issue
    4
  • fYear
    2012
  • fDate
    4/1/2012 12:00:00 AM
  • Firstpage
    902
  • Lastpage
    908
  • Abstract
    A scaling theory of double-gate interband tunnel field-effect transistors (TFETs) using a physics-based 2-D analytical model is presented. Ignoring the mobile charge in the channel, the electrostatic potential profile and electric field are analytically solved, and the current is calculated by integrating the band-to-band tunneling generation rate over the volume of the device. The analytical model has excellent agreement with the numerical results obtained from a commercial simulator and atomistic nonequilibrium Green function simulations for both heterojunction and homojunction TFETs. The analytical model allows us to quantitatively extract the electrostatic scaling lengths in TFETs and compare the short-channel effect of TFETs with that of MOSFETs. We conclude that double-gate TFETs exhibit superior short-channel performance than their MOSFETs counterparts at a longer gate length (greater than four times the scaling length), but the scalability of the TFETs degrades at a faster rate than MOSFETs do at smaller gate lengths (less than four times the scaling length).
  • Keywords
    Green´s function methods; insulated gate field effect transistors; tunnel transistors; atomistic nonequilibrium Green function simulation; band-to-band tunneling generation rate; commercial simulator; double-gate interband tunnel field-effect transistor; electrostatic potential profile; electrostatic scaling length; heterojunction TFET; homojunction TFET; physics-based 2D analytical model; scaling length theory; short-channel performance; Analytical models; Electric potential; Electrostatics; Heterojunctions; Logic gates; MOSFETs; Tunneling; Analytical model; drain-induced barrier lowering (DIBL); drain-induced barrier thinning (DIBT); scalability; short-channel effect; tunnel field-effect transistor (TFET);
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2012.2183875
  • Filename
    6158624