DocumentCode :
1458707
Title :
A novel coplanar amorphous silicon thin-film transistor using silicide layers
Author :
Kim, Sung Ki ; Choi, Young Jin ; Kwak, Won Kyu ; Cho, Kyu Sik ; Jang, Jin
Author_Institution :
Dept. of Phys., Kyung Hee Univ., Seoul, South Korea
Volume :
20
Issue :
1
fYear :
1999
Firstpage :
33
Lastpage :
35
Abstract :
A novel, coplanar, hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) was fabricated by depositing a triple layer consisting of a-Si:H, silicon-nitride, and a-Si:H. After patterning the top two layers in the gate stack, the devices were doped and a 30 nm Ni layer was deposited. The devices were then annealed for 1 h at 230/spl deg/C to form self-aligned, low resistive Ni-silicide. The fabricated coplanar a-Si:H TFT exhibits a field effect mobility of 0.6 cm/sup 2//Vs, a threshold voltage of 2 V, a subthreshold slope of 0.4 V/dec, and an on/off current ratio of /spl sim/10/sup 7/.
Keywords :
amorphous semiconductors; annealing; carrier mobility; elemental semiconductors; hydrogen; liquid crystal displays; semiconductor device measurement; silicon; thin film transistors; 1 hour; 2 V; 230 C; 30 nm; AMLCD; Ni layer; NiSi-SiN-Si:H; a-Si:H coplanar TFT; annealing; device doping; field effect mobility; gate stack; on/off current ratio; patterning; self-aligned low resistive Ni-silicide; silicide layers; subthreshold slope; threshold voltage; triple layer deposition; Active matrix liquid crystal displays; Amorphous silicon; Annealing; Degradation; MOSFETs; Physics; Production; Silicides; Thin film transistors; Threshold voltage;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/55.737565
Filename :
737565
Link To Document :
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