VLSI implementation of a signal recognition and code acquisition algorithm for CDMA packet receivers

The widespread application of direct-sequence spread-spectrum code division multiple access (DS/SS-CDMA) to wireless communication systems asks for ever faster and more reliable real-time signal processing operations to be performed by highly integrated and low-power consumption digital receivers. One of the most critical signal processing tasks to be performed by the DS/SS-CDMA receiver is signal presence detection and code epoch estimation. This paper deals with the design and realization of an application-specific integrated-circuit (ASIC) for fast signal recognition and code acquisition (SR/CA) in packet DS/SS-CDMA receivers operating in a satellite or terrestrial radio network. In particular, we show how a parallel acquisition circuit can be effectively implemented on a single-chip with a 1.0-μm CMOS technology according to the specifications of the ARCANET Ku-band CDMA VSAT satellite network sponsored by the European Space Agency (ESA). It is shown that the ASIC performance closely follows analytical predictions