Title :
Efficient implementation of multiplicative congruential generators in FPGAs
Author_Institution :
Fac. of Electron. & Telecommun., Poznan Univ. of Technol., Poznan, Poland
Abstract :
This paper presents a universal hardware implementation of a pseudorandom number generator family based on a multiplicative congruential generator (MCG) with modulus 231-1. The algorithm optimised both the multiplication and modulo 231-1 operation. The design was specified in Verilog and implemented on a Xilinx Field Programmable Gate Array (FPGA) device XC6SLX45. A single generator takes up about 130 slices and can produce up to 4.169 Gbits per second. Implemented generators are not secure themselves, but they can be used in cryptography with additional processing and by using several different generators in parallel.
Keywords :
cryptography; field programmable gate arrays; random number generation; FPGA; MCG; Verilog; XC6SLX45; cryptography; efficient implementation; multiplicative congruential generators; parallel generators; pseudorandom number generator; universal hardware implementation; xilinx field programmable gate array; Algorithm design and analysis; Clocks; Decision support systems; Field programmable gate arrays; Generators; Hardware; Hardware design languages; FPGA implementation; MCG; random number generator;
Conference_Titel :
Signals and Electronic Systems (ICSES), 2014 International Conference on
Conference_Location :
Poznan
DOI :
10.1109/ICSES.2014.6948737
