Cycling-induced threshold-voltage instabilities in nanoscale NAND flash memories: Sensitivity to the array background pattern

This work investigates cycling-induced threshold-voltage instabilities in nanoscale NAND Flash cells as a function of the array background pattern. Instabilities are mainly the result of charge detrapping from the cell tunnel oxide during post-cycling idle/bake periods and represent one of the major reliability issues for multi-level devices. Results reveal, first of all, that instabilities in a (victim) cell do not depend only on its memory state, but also on the memory state of its first neighboring (aggressor) cells. This new interference effect is shown to decrease in magnitude for higher threshold-voltage levels of the victim cell and to come mainly from an interaction with aggressor cells in the bit-line direction. From this evidence, a physical picture explaining the phenomenon and its main dependences is provided.