A practical floating-gate Muller-C element using vMOS threshold gates

Author

Rodriguez-Villegas, E. ; Huertas, G. ; Avedillo, M.J. ; Quintana, J.M. ; Rueda, A.

Author_Institution

Inst. de Microelectron., Seville Univ., Spain

Volume

48

Issue

1

fYear

2001

fDate

1/1/2001 12:00:00 AM

Firstpage

102

Lastpage

106

Abstract

This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation

Keywords

MOS logic circuits; delays; logic CAD; logic simulation; neural chips; threshold logic; VMOS threshold gates; area; delay; digital circuits; floating-gate Muller-C element; logic design techniques; low-cost design technique; power consumption; threshold logic gates; CMOS logic circuits; CMOS technology; Delay; Digital circuits; Logic circuits; Logic design; Logic gates; MOSFETs; Potential well; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.913193

Filename

913193