Title :
Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI
Author :
Akyel, Kaya Can ; Ciampolini, L. ; Thomas, O. ; Turgis, D. ; Ghibaudo, Gerard
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
This work investigates the impact of Random Telegraph Signal (RTS) noise on a 6 Transistors single P-well Static Random Access Memory (6T-SRAM) manufactured in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB FD-SOI) technology. A SPICE-level bias-and time-dependent RTS model peculiar to UTBB FD-SOI, which considers both front- and back-gate of the device as RTS sources, is presented. The Bit-Error-Rate is evaluated on silicon dies through the write-ability (WA) failure criterion and with a dedicated back-biasing strategy. Simulations evidence the role of RTS-induced dynamic variability with respect to process variability and show a good agreement with measurements.
Keywords :
SRAM chips; error statistics; integrated circuit noise; silicon; silicon-on-insulator; 6 transistors single P-well SRAM; 6T-SRAM; RTS noise; RTS-induced dynamic variability; SPICE; Si; UTBB FD-SOI technology; back-biasing strategy; back-gate; bias-and time-dependent RTS model; bit-error-rate; buried oxide fully-depleted silicon-on-insulator; front-gate; high-density SRAM; process variability; random telegraph signals; silicon dies; size 28 nm; static random access memory; ultra-thin body; write-ability failure criterion; Bit error rate; Dielectrics; Integrated circuit modeling; Logic gates; Mathematical model; Random access memory; Transistors; FD-SOI; RTS; Random Telegraph Signal; SRAM;
Conference_Titel :
Solid State Device Research Conference (ESSDERC), 2014 44th European
Conference_Location :
Venice
Print_ISBN :
978-1-4799-4378-4
DOI :
10.1109/ESSDERC.2014.6948766
