A 1.8~3.2-GHz fully differential GaAs MESFET PLL

Author

Cheung, Tae-Sik ; Lee, Bhum-Cheol ; Choi, Eun-Chang ; Choi, Woo-Young

Author_Institution

Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea

Volume

36

Issue

4

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

605

Lastpage

610

Abstract

A 1.8~3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74~3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8~3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz

Keywords

III-V semiconductors; MESFET integrated circuits; asynchronous transfer mode; circuit tuning; clocks; gallium arsenide; jitter; phase locked loops; very high speed integrated circuits; voltage-controlled oscillators; 0.5 micron; 1.8 to 3.2 GHz; GaAs; GaAs MESFET integrated circuit; asynchronous transfer mode clock generation; differential charge pump; differential voltage controlled oscillator; fully differential phase locked loop; hold characteristics; jitter; tuning range; very high speed integrated circuit; Charge pumps; Delay effects; Frequency; Gallium arsenide; Inverters; MESFETs; Phase locked loops; Propagation delay; Tuning; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.913738

Filename

913738