A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell

Author

Lin, Perng-Fei ; Kuo, James B.

Author_Institution

Nat. Taiwan Univ., Taipei, Taiwan

Volume

36

Issue

4

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

666

Lastpage

675

Abstract

This paper reports a 1-V 128-kb four-way set-associative CMOS cache memory implemented by a 0.18-μm CMOS technology using wordline-oriented tag-compare (WLOTC) structure with the 10-transistor tag cell usually for content-addressable memory (CAM) for low-voltage low-power VLSI system application. Owing to the WLOTC structure with the CAM 10-transistor tag cell for accommodating the one-step hit/miss generation and the dynamic pulse generators for realizing read-enable signals, a small hit access time (3.5 ns), low power consumption (4.1 mW at 50 MHz), and good expansion capability without sacrificing speed have been obtained

Keywords

CMOS memory circuits; VLSI; cache storage; content-addressable storage; low-power electronics; memory architecture; pulse generators; 0.18 micron; 1 V; 128 kbit; 3.5 ns; 4.1 mW; 50 MHz; content-addressable-memory; dynamic pulse generators; expansion capability; four-way set-associative CMOS cache memory; hit access time; low-voltage low-power VLSI system; one-step hit/miss generation; power consumption; read-enable signals; wordline-oriented tag-compare structure; CADCAM; CMOS technology; Cache memory; Computer aided manufacturing; Energy consumption; Low voltage; Paper technology; Pulse generation; Signal generators; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.913745

Filename

913745