Title :
On-chip ESD protection design by using polysilicon diodes in CMOS process
Author :
Ker, Ming-Dou ; Chen, Tung-Yang ; Wang, Tai-Ho ; Wu, Chung-Yu
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
4/1/2001 12:00:00 AM
Abstract :
A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is proposed in this paper. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-puIse (TLP) generator to investigate its ESD robustness. Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original ~300 V to become ⩾3 kV. This design has been practically applied in a mass-production smart-card IC
Keywords :
CMOS integrated circuits; doping profiles; electrostatic discharge; integrated circuit design; integrated circuit modelling; integrated circuit reliability; semiconductor device breakdown; smart cards; 3 kV; CMOS process; ESD robustness; VDD-to-VSS clamp circuit; clamp devices; doping concentration; forward-bias conditions; human-body-model ESD robustness; mass-production smart-card IC; on-chip ESD protection design; polysilicon diodes; process splits; reverse-bias conditions; secondary breakdown current; transmission-line-pulse generator; CMOS process; Clamps; Current measurement; Design optimization; Diodes; Doping; Electric breakdown; Electrostatic discharge; Protection; Robustness;
Journal_Title :
Solid-State Circuits, IEEE Journal of
