CMOS circuit verification with symbolic switch-level timing simulation

Author

McDonald, Clayton B. ; Bryant, Randal E.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

20

Issue

3

fYear

2001

fDate

3/1/2001 12:00:00 AM

Firstpage

458

Lastpage

474

Abstract

Symbolic switch-level simulation has been extensively applied to the functional verification of complementary metal-oxide-semiconductor (CMOS) circuitry. We have extended this technique to account for real-valued data-dependent delay values and have developed a novel mechanism for symbolically computing data-dependent Elmore delays. We present our symbolic simulation and delay calculation algorithms and discuss their application to the timing and functional verification of full-custom transistor-level CMOS circuitry

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; binary decision diagrams; circuit simulation; delays; discrete event simulation; formal verification; integrated circuit modelling; symbol manipulation; timing; CMOS circuit verification; data-dependent Elmore delays; delay calculation algorithms; full-custom transistor-level CMOS circuitry; real-valued data-dependent delay values; symbolic switch-level timing simulation; Boolean functions; Circuit simulation; Computational modeling; Delay; Discrete event simulation; FETs; Inverters; Sociotechnical systems; Switching circuits; Timing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.913762

Filename

913762