T2A: Clock implementation: A question of timing

In digital ASIC design, clocks are complicated by timing. This tutorial looks at clock constraints in timing analysis as the affect the hierarchical design flow and timing validation across process variation. The focus is upon how constraints support construction, from a practical perspective forged over many years working on clock tree implementation. This tutorial would cover the following important topics in clock implementation: Timing with propagated clocks and ideal clocks: background on timing report structure and setup/hold particularly on IO paths, assumption of synchronous design; Virtual clocks for IO timing: role to keep path constraints unchanged, standard calculation methods for its latency, problems with values in standard blockmodels, timing impact in using Max rather than average latency.; Refocus on role of virtual-clock latency in hierarchical design; description of improved approach; Propagation on pins rather than clock objects to avoid updating constraints after synthesis. Note exception where virtual clock required.; Description of the role of float pins in clock tree synthesis; Using latency values to: a) anticipate clock-gate-enable timing and b) enable single ETMs for macros.; Why memories need a float pin and an early latency; Types of variation contrasting global vs local: discussion of transistor and parasitic corners.; Demonstration of extent of variation by taking a simple repeater chain and varying the segment drivers; consequence to clock design ⇒ need to balance not just delay but also sources of delay, including within macro design.; Difference between Setup and Hold closure and how these motivate corners for design sign-off; hold is variation about the mean - setup is from the edge of the curve.; Setup is slowest corner: temperature effect (slows interconnect, hastens transistors except when it does not!) - also check FAST wafers if voltage lowered for power saving.; Hold is NOT a feature of fast data-paths but rather is - ominated by clock skew which is an outcome of variation ⇒ worst corners are corners away from where clock optimized; explanation of hold risk from scan reordering and how it is minimized; Role of derates (OCV and AOCV) and clock uncertainty; increase of hold uncertainty is catastrophic.; Wire design: Signal EM avoidance ⇒ wider metal; Cross-talk avoidance (effect of cross-talk on timing in general - on macros in particular) ⇒ spacing vs shielding: latency, resource use, power (target skew); Early description to enable tool anticipation of final parasitics and resource allocation.