T1B: Wireless NoC as interconnection backbone for multicore chips: Promises and challenges

The continuing progress and integration levels in silicon technologies make complete end-user systems on a single chip possible. This massive level of integration makes modern multi-core chips all pervasive in domains ranging from weather forecasting, astronomical data analysis, and biological applications to consumer electronics and smart phones. NoCs have emerged as communication backbones to enable a high degree of integration in multi-core SoCs. Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between far-apart blocks causes high latency and power consumption. The latency, power consumption, and interconnect routing problems of NoCs can be simultaneously addressed by replacing multi-hop wired paths with high-bandwidth single-hop long-range wireless links. In this tutorial, we will present an overview of the various wireless NoC (WiNoC) architectures proposed so far designed in traditional 2D IC substrate. After this, we introduce how high bandwidth and low power WiNoC architectures can be designed by incorporating the small-world architecture. We will present detailed performance evaluation and necessary design trade-offs for the small-world WiNoCs with respect to their conventional wireline counterparts. We will also discuss different media access control (MAC) mechanisms and routing protocols used for planar WiNoCs so far. We discuss design of various suitable MACs, including token passing, CDMA, FDMA, and time hopping, among others. To sustain the predicted WiNoC performance, a deadlock-free routing algorithm must be designed. The routing protocol also needs to be simple without incurring excessive power, area and latency overheads. We also present performance evaluation of WiNoCs with respect to various other emerging NoC architectures, like 3D, Photonics and RF-I. The continuing progress and integration levels in silicon technolo- ies make complete end-user systems on a single chip possible. This massive level of integration makes modern multi-core chips all pervasive in domains ranging from weather forecasting, astronomical data analysis, and biological applications to consumer electronics and smart phones. NoCs have emerged as communication backbones to enable a high degree of integration in multi-core SoCs. Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between far-apart blocks causes high latency and power consumption. The latency, power consumption, and interconnect routing problems of NoCs can be simultaneously addressed by replacing multi-hop wired paths with high-bandwidth single-hop long-range wireless links. In this tutorial, we will present an overview of the various wireless NoC (WiNoC) architectures proposed so far designed in traditional 2D IC substrate. After this, we introduce how high bandwidth and low power WiNoC architectures can be designed by incorporating the small-world architecture. We will present detailed performance evaluation and necessary design trade-offs for the small-world WiNoCs with respect to their conventional wireline counterparts. We will also discuss different media access control (MAC) mechanisms and routing protocols used for planar WiNoCs so far. We discuss design of various suitable MACs, including token passing, CDMA, FDMA, and time hopping, among others. To sustain the predicted WiNoC performance, a deadlock-free routing algorithm must be designed. The routing protocol also needs to be simple without incurring excessive power, area and latency overheads. We also present performance evaluation of WiNoCs with respect to various other emerging NoC architectures, like 3D, Photonics and RF-I.